Power Reduction by Clock Gating Technique. Nandita Srinivasana, ha, , ,. Swetha Sri *, Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Clock Gating is a technique that can be used to control power dissipated by Clock net. In synchronous digital circuits the clock net is responsible for significant part of power dissipation (up to 40%) [2]. Clock gating reduces the unwanted switching on the parts of clock net by disabling the clock.


CLOCK GATING TECHNIQUES EPUB

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CLOCK GATING TECHNIQUES EPUB


Moreover, since only one operation, either write clock gating techniques read, is allowed at a time, we need another input to specify whether we are writing to or reading from the file.

CLOCK GATING TECHNIQUES EPUB

To perform the read operation, we again need to select the target row. This is achieved using a multiplexer at the output of the register file.

In clock gating techniques words, when in read mode, we are specifying the current value of a register as its next value. To this end, a two-input multiplexer is placed at the input of each row.

How to Reduce Power Consumption with Clock Gating

During the read operation, the select input of all these multiplexers is logic low and, hence, the content of each DFF is returned to its input. Read Mode Wastes Power Read mode is not efficient from power consumption point clock gating techniques view. This requires applying the clock signal to a large number of DFFs.

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How can we avoid charging this capacitance? During the read operation, the content of the register file must not change.

The approach shown above ensures that the register values will not change, but we can clock gating techniques the same thing by simply switching off the clock signal. This technique, called clock gating, can significantly reduce power consumption.

However, it can lead to serious problems too.

When en is logic high, the gated clock, gck, will be equal to ck. This is the basic concept of clock gating.

But, what if en is logic clock gating techniques Should gck be high or low in this case? Coded into the register transfer level RTL code as enable conditions that can be automatically translated into clock gating logic by synthesis tools fine grain clock gating.

Clock gating - Wikipedia

Inserted into the design manually by the RTL designers typically as module level clock gating by instantiating library specific integrated clock gating ICG cells to clock gating techniques the clocks of specific modules or registers. Semi-automatically inserted into the RTL by automated clock gating tools.

These typically also offer sequential clock gating optimisations. Any RTL modifications to improve clock gating will result in functional changes to the design since the registers will now hold different values which need to be verified. Although asynchronous circuits by definition do not have a "clock", the term perfect clock gating is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry.

As the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit: At one end is the manual gating of clocks by software, where a driver enables or disables clock gating techniques various clocks used by a given idle controller.



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